1. Field of the Invention
The present invention relates to phase-locked loop circuits, and particularly to technique for reducing a time required for lock-up of the phase-locked loop circuit which operates intermittently.
2. Description of the Background Art
FIG. 13 is a block diagram showing the structure of a conventional phase-locked loop circuit 200. A reference oscillator 1 outputs oscillation signal having a constant frequency which is relatively low. This is divided by a reference divider 2 and then a reference signal f.sub.REF having a constant frequency is obtained.
A voltage-controlled oscillator 8 outputs a raw signal f.sub.RAW having a relatively high frequency, which is divided by a prescaler 3 and a programmable divider 4 at a certain ratio to be a signal to be measured f.sub.0. The phase-locked loop circuit 200 makes control so that the signal to be measured f.sub.0 always has the same frequency as that of the reference signal f.sub.REF to stabilize the frequency of the raw signal f.sub.RAW having the relatively high frequency.
The reference signal f.sub.REF and the signal to be measured f.sub.0 are inputted to a phase difference detecting means composed of a phase comparator 5, a charge pump 6 and a low-pass filter 7. Then, a phase difference voltage V.sub.P is provided to the voltage-controlled oscillator 8 on the basis of a phase difference between the reference signal f.sub.REF and the signal to be measured f.sub.0. The voltage-controlled oscillator 8 outputs the raw signal f.sub.RAW having a frequency based on the phase difference voltage.
Accordingly, changing the frequency of the signal to be measured f.sub.0 so that the phase difference between the reference signal f.sub.REF and the signal to be measured f.sub.0 disappears makes the frequency of the signal to be measured f.sub.0 equal to that of the reference signal f.sub.REF. It is easy to stabilize the frequency of the reference signal f.sub.REF having the relatively low frequency, and further, the stability of the raw signal f.sub.RAW having the relatively high frequency is enhanced by using the phase-locked loop circuit 200.
Such a phase-locked loop circuit is used to apply the raw signal f.sub.RAW to a frequency synthesizer unit for transmit/receive of a portable telephone, for example. In the portable telephone in which the time-division telegraphy is performed, for example, the raw signal f.sub.RAW is not always required for the frequency synthesizer unit for transmit/receive.
It is necessary to divide the raw signal f.sub.RAW to generate the signal to be measured f.sub.0 as described above to stabilize the raw signal f.sub.RAW with the relatively high frequency in reference to the reference signal f.sub.REF which is stable because of its relatively low frequency.
Now, an ECL circuit with bipolar transistor is usually required to divide a high frequency. However, since the ECL circuit has large consumption power, dividing is performed in two steps, where only the prescaler 3 for dividing to a frequency which can be processed by a divider composed of CMOS circuitry having small consumption power is composed of ECL circuitry and dividing thereafter is made by the programmable divider 4 composed of CMOS circuitry, for example.
Accordingly, most of the power consumed in the phase-locked loop circuit is the power consumed in the prescaler 3 composed of the ECL circuitry. Therefore, an attempt is made to reduce the consumption power by turning ON/OFF the prescaler 3 to match with the time-division telegraphy. An operation control signal S.sub.0 inputted to the prescaler 3 controls ON/OFF of the operation of the prescaler 3.
However, while ON/OFF of the operation of the prescaler 3 is controlled by the operation control signal S.sub.0, the timing of activation of the operation control signal S.sub.0 (turning-on of the operation of the prescaler 3) with respect to the reference signal f.sub.REF is indefinite. This is because the phase of the reference signal f.sub.REF and the timing of the time-division telegraphy has no relation.
FIG. 14 is a timing chart showing the relation among the reference signal f.sub.REF, the signal to be measured f.sub.0 and the operation control signal S.sub.0 in the phase-locked loop circuit 200. When the operation control signal S.sub.0 goes "H" and then the operation of the prescaler 3 turns on, the prescaler 3 starts dividing the raw signal f.sub.RAW. While it is further divided by the programmable divider 4 to be the signal to be measured f.sub.0, there is a difference in phase (or time) .delta. between the timing of the first transition of the signal to be measured f.sub.0 from "H" to "L" and the timing of the transition of the reference signal f.sub.REF.
Now, the phase (or time) .delta. is indefinite depending on the timing of activation of the operation control signal S.sub.0 with respect to the reference signal f.sub.REF. Accordingly, a time required to match the frequency of the signal to be measured f.sub.0 with that of the reference signal f.sub.REF, i.e., to lock up, is indefinite.
It is necessary to intermittently transmit and receive at predetermined intervals and with predetermined lengths in the time-division telegraphy, and the frequency of the signal to be measured f.sub.0 must be matching with that of the reference signal f.sub.REF in the periods of transmission and reception. Accordingly, the operation control signal S.sub.0 must be activated prior to the time of transmission and reception by a time longer enough than the phase (or time) .delta.. It means that the prescaler 3 consumes power in a period longer than the period of transmission and reception.
As described above, when the conventional phase-locked loop circuit 200 is used, there is a problem that the power consumption of the prescaler 3 can not be suppressed enough.